Target type ieee.std_logic_1164.STD_LOGIC_VECTOR in variable assignment is different from expression type ieee.std_logic_1164.STD_ULOGIC. 1

Target type ieee.std_logic_1164.STD_LOGIC_VECTOR in variable assignment is different from expression type ieee.std_logic_1164.STD_ULOGIC.

type t_g is array (1 downto 1, 3 downto 1)of integer;
signal g: t_g;

Here is what the above code is Doing:
1. We are creating a signal called g.
2. We are creating a type called t_g.
3. We are telling the compiler that g is of type t_g.
4. We are telling the compiler that t_g is an array of integers.
5. We are telling the compiler that t_g is a 2-dimensional array.
6. We are telling the compiler that t_g has 3 rows and 1 column.
7. We are telling the compiler that t_g has 1 row and 3 columns.

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